Browsing by Author "Aktan, Mustafa."

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    High level power efficient synthesis of FIR based digital systems
    (Thesis (Ph.D.)-Bogazici University. Institute for Graduate Studies in Science and Engineering, 2008., 2008.) Aktan, Mustafa.; Dündar, Günhan,
    Digital filters are the most frequently used elements in signal processing applications. Among digital filters, FIR filters are preferred due to their stability, easily achievable linear-phase property, and low quantization wordlength sensitivity. All these desirable properties come with a drawback: increased computational workload. This, in turn, leads to excessive amount of power dissipation which is a bottleneck for today’s low power demanding applications. In this work, a low-power design methodology for the design of FIR filters is proposed. The methodology is implemented in a software tool where the user gives only the characteristics of the FIR filter. The tool generates the power optimized circuit/coefficient set depending on the type of realization of the filter: parallel/sequential. For the parallel realization using constant coefficients, power is related to the number of nonzero digits in the binary notation of the filter coefficients. On the other hand, the sequential realization of FIR filters is done on programmable processors where coefficients are successively applied to the inputs of a multiply accumulate unit. Hence, switching activity between successively applied coefficients is important for low power design. In this context, a novel algorithm for the design of low-power and hardware efficient linearphase FIR filters is proposed which is the main contribution of this work. The algorithm finds filter coefficients with reduced complexity (number of ones in coefficients, switching activity between coefficients) given the filter frequency response characteristics. Although the worst case run time of the algorithm is exponential, its capability to find appreciably good solutions in a reasonable amount of time makes it a desirable CAD tool for designing low-power and hardware efficient FIR filters. The superiority of the algorithm on existing methods in terms of design time, hardware complexity, and power performance is shown with several design examples for both parallel and sequential realizations of FIR filters.
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    Logic-level pover estimation in CMOS VLSI circuits
    (Thesis (M.S.) - Bogazici University. Institue for Graduate Studies in Science and Engineering, 2001., 2001.) Aktan, Mustafa.; Dündar, Günhan,
    In this thesis, a power estimator for both combinational and sequential CMOS logic circuits is presented. The estimation method is probabilistic in nature and is based on tagged probabilistic simulation (TPS). TPS can handle large circuits efficiently with the implementation of the local BDD approach.TPS was originally developed for power estimation in combinational circuits. In this work it is extended to handle sequential circuits as well. Recently developed methods use symbolic simulation equations to estimate power in sequential circuits. The symbolic simulation method is not applicable to the local BDD approach. To overcome this bottleneck a simple method based on thecalculation of the transition probabilities is proposed. The method is efficient as far as speed is concerned but has accuracy problems when compared to the symbolic simulation method.