A synthesizable core generator design in VHDL for the motorola 68XXX family of microprocessors

Abstract

The goal of this project is to implement a core generetor to create a Motorola68000 op-code compatible microprocessor capable of being synthesized using FPGA. The CPU is specified fully in VHDL and is designed to emulate the functionality of theMC68000 in terms of instruction set decoding, operand addressing and bus operation.The ultimate target device is fully enhanced, self testing, memory and cache optimized,improved version of the Motorola 68000 microprocessor. The core generator is to be fully automatic without any need of editing the VHDL code created. The core generatoris to be functional, effective and modular for using with any microprocessor design. Asa result of this, a large emphasis has been placed on how to create the microprocessorstructures especially the instruction sets, arithmetic logic units and memory structureusing a core generator.