Logic-level pover estimation in CMOS VLSI circuits

Abstract

In this thesis, a power estimator for both combinational and sequential CMOS logic circuits is presented. The estimation method is probabilistic in nature and is based on tagged probabilistic simulation (TPS). TPS can handle large circuits efficiently with the implementation of the local BDD approach.TPS was originally developed for power estimation in combinational circuits. In this work it is extended to handle sequential circuits as well. Recently developed methods use symbolic simulation equations to estimate power in sequential circuits. The symbolic simulation method is not applicable to the local BDD approach. To overcome this bottleneck a simple method based on thecalculation of the transition probabilities is proposed. The method is efficient as far as speed is concerned but has accuracy problems when compared to the symbolic simulation method.