Low power consumption continuous time sigma-delta modulator design

Abstract

Mobile electronic devices have important roles in our daily lives. While they are getting smaller, their functionality is increasing. As the charge capacity of the batteries is limited, it should be spent e ciently. Low power consumption designs respond to high power demand of these multifunctional devices. Data converters which act as the interface between analog and digital signals are used in most electronic devices. There are many analog to digital converter topologies with respect to the application type used in. Sigma-Delta ADCs are generally preferred for low power consumption and high signal-to-noise ratio. Type of a Sigma-Delta ADC is determined by the lter/integrator block. Di erent types of continuous time integrators are presented in system level. Derivation and detailed noise analysis of current-mode di erential integrators are demonstrated in this thesis. Feedback analysis is performed and compared with simulations. Simulation results are presented verifying theoretical results. The e ect of enhancing DC gain of the integrator on the noise is examined. It is concluded that the positive feedback in the integrator circuit causes high noise levels. A 2nd order CT current-mode - ADC is designed and manufactured in UMC 130nm technology. Post-layout simulation and measurement results are compared. Observed noise levels on both simulations and tests are high because of the positive feedback e ect of current-mode di erential integrator used in the lter block.