Analog circuit optimization with hierarchical genetic algorithms - 3rd order low-pass butterworth filter example

Abstract

In the several previous studies, various kinds of Hierarchical Genetic Algorithm structures have been used to solve complex problems. In this thesis, a master-slave mode, two-layered Hierarchical Genetic Algorithm was designed to optimize an implementable complex integrated circuit. Our expectations from two-layered proposed HGA is to minimize the total process time, to reach the same solution quality with standard HGA in complex problems and to increase the compatibility to any other topology by working two modules collaboratively with each other. In the example chosen in the thesis, the upper module (master module) will optimize a 3rd order active low-pass Butterworth filter and the lower module (slave module) will optimize the OPAMPs (MOS technology based integrated circuit) in the filter circuit, with SPICE based simulation. Thanks to this algorithm which will be realized by the proposed HGA, solutions can be implemented with current MOS technologies and the same result quality can be obtained with standard HGA and a low total process time is obtained such as in the Genetic Algorithm.