Development of a flexible analog IP library
dc.contributor | Graduate Program in Electrical and Electronic Engineering. | |
dc.contributor.advisor | Dündar, Günhan, | |
dc.contributor.author | Kaya, Ezgi. | |
dc.date.accessioned | 2023-03-16T10:19:29Z | |
dc.date.available | 2023-03-16T10:19:29Z | |
dc.date.issued | 2018. | |
dc.description.abstract | In this thesis, an analog circuit synthesis and design assistant tool is proposed. The developed tool employs an SPEA2 algorithm as a multi-objective optimization engine to generate Pareto-optimal Fronts (PoF) for a given design problem. An analog library serving as analog IP, was also constructed, which includes pre-optimized PoFs and extracted PoF models for different loading and power limitation conditions. Thus, the user can either generate a new PoF for her/his problem or use the pre-existing PoFs as well as the extracted models without running any optimization step. The developed tool can also be utilized for feasibility checking of a circuit, performance prediction, and topology selection. The tool gives the opportunity of visualization of the design solutions, by allowing the user to verify the Pareto-optimal points in the test benches, to observe the design specifications of a specific design solution. A graphical user interface (GUI) is developed to combine all these utilities. To demonstrate the developed tool, two different OTA topologies and a comparator are examined and all parts of the tool were discussed in detail. Finally, the POFs of the OTA and comparator circuits are composed to obtain the PoF of a higher-level block. | |
dc.format.extent | 30 cm. | |
dc.format.pages | xiv, 50 leaves ; | |
dc.identifier.other | EE 2018 K37 | |
dc.identifier.uri | https://digitalarchive.library.bogazici.edu.tr/handle/123456789/12931 | |
dc.publisher | Thesis (M.A.) - Bogazici University. Institute for Graduate Studies in the Social Sciences, 2018. | |
dc.subject.lcsh | Analog-to-digital converters. | |
dc.title | Development of a flexible analog IP library |
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