FPMA design in submicron technologies with digital error correction

Abstract

The trend in VLSI systems towards System-On-Chip (SOC) leads to integration of digital and analog circuits on a single chip. The communication between the digital and analog blocks is employed by A/D and D/A converters. Also, digital error correction with the urge of submicron technologies is mostly used in these converters to achieve desired resolution, linearity, speed and low power. In this thesis, eld programmable digital and analog array architectures and their applications are introduced. Digitally assisted architecture types for A/D and D/A converters are demonstrated and best suited architectures for TSMC 90nm technology are chosen. An 8-bit 1GSample/s current steering based DAC design is realized in TSMC 90nm technology. A self calibration technique is applied to the DAC as a digital error correction scheme. The performance improvement of the DAC after digital error correction is observed and the results are obtained using Mentor Graphics software tools and MATLAB.|Keywords : Digital error correction, Analog integrated circuits