An efficient flash translation layer implementation for nor flash memory
| dc.contributor | Graduate Program in Electrical and Electronic Engineering. | |
| dc.contributor.advisor | Başkaya, Faik. | |
| dc.contributor.author | Çam, Fatih. | |
| dc.date.accessioned | 2025-04-14T12:25:48Z | |
| dc.date.available | 2025-04-14T12:25:48Z | |
| dc.date.issued | 2023 | |
| dc.description.abstract | As technology develops day by day, the amount of data that electronic systems need to manage is increasing in direct proportion. Especially in embedded systems, the necessity to use space efficiently does not allow flash memories used as storage units to exceed a certain size. The fact that the technology on which flash memories are built has a certain lifetime has made it necessary to use these technologies in the most effective way. The algorithm developed as a solution to this problem is the flash translation layer (FTL). Different FTL algorithms have been proposed over the years, and these algorithms have led to some disadvantages along with many advantages. The aim of this thesis is to present a much simpler and implementable FTL algorithm, which is different from the complex algorithms proposed before, and which also shows high success. For read and write operations, the target page address is found directly from the mapping table and the operation is performed. In the write operation, the target page address is determined by the value from the random number generator. If data has been written to this flash address before, the data at this address is moved to the next free flash address and the data to be written is written to the page address from the random number generator. With this method, page writing is carried out quickly and effectively. The algorithm was implemented on the FPGA and tested over UART with test software designed on the computer. The results of the test application showed that the designed algorithm used flash memory pages with a regular distribution and the success rate was 98%. In addition, only one flash memory page sacrifice was sufficient to use this algorithm. Thus, this study did not cause space loss in flash memory, unlike other algorithms. | |
| dc.format.pages | xiv, 68 leaves | |
| dc.identifier.other | Graduate Program in Electrical and Electronic Engineering. TKL 2023 U68 PhD (Thes LING 2023 K89 | |
| dc.identifier.uri | https://digitalarchive.library.bogazici.edu.tr/handle/123456789/21525 | |
| dc.publisher | Thesis (M.S.) - Bogazici University. Institute for Graduate Studies in Science and Engineering, 2023. | |
| dc.subject.lcsh | Flash memories (Computers) | |
| dc.subject.lcsh | Static random access memory. | |
| dc.title | An efficient flash translation layer implementation for nor flash memory |
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