Development of a flexible analog IP library - Kaya, Ezgi. (Thesis (M.A.) - Bogazici University. Institute for Graduate Studies in the Social Sciences, 2018., 2018)
In this thesis, an analog circuit synthesis and design assistant tool is proposed. The developed tool employs an SPEA2 algorithm as a multi-objective optimization engine to generate Pareto-optimal Fronts (PoF) for a given design problem. An analog library serving as analog IP, was also constructed, which includes pre-optimized PoFs and extracted PoF models for diﬀerent loading and power limitation conditions. Thus, the user can either generate a new PoF for her/his problem or use the pre-existing PoFs as well as the extracted models without running any optimization step. The developed tool can also be utilized for feasibility checking of a circuit, performance prediction, and topology selection. The tool gives the opportunity of visualization of the design solutions, by allowing the user to verify the Pareto-optimal points in the test benches, to observe the design speciﬁcations of a speciﬁc design solution. A graphical user interface (GUI) is developed to combine all these utilities. To demonstrate the developed tool, two diﬀerent OTA topologies and a comparator are examined and all parts of the tool were discussed in detail. Finally, the POFs of the OTA and comparator circuits are composed to obtain the PoF of a higher-level block.
Keywords: Analog-to-digital converters.