Realization and modeling of water-gated field effect transistors (WG-FET) using 16-NM-THICK single crystalline silicon film and their circuit applications
| dc.contributor | Ph.D. Program in Electrical and Electronic Engineering. | |
| dc.contributor.advisor | Mutlu, Şenol. | |
| dc.contributor.author | Sönmez, Bedri Gürkan. | |
| dc.date.accessioned | 2023-03-16T10:25:19Z | |
| dc.date.available | 2023-03-16T10:25:19Z | |
| dc.date.issued | 2017. | |
| dc.description.abstract | This thesis covers realization and modeling of novel water-gated field effect transistors (WG-FETs) which use 16-nm-thick single crystalline silicon lm as active layer. WG-FET devices utilize electrical double layer (EDL) structure as a replacement of gate insulator and operate in the non-Faradaic region (under 1 V) without causing any oxidation/reduction reactions. Performance parameters based on voltage distribution on EDL are extracted and current-voltage relations are modeled. Various WG-FET devices with both probe- and planar-gate setups are simulated, fabricated and tested. E ects of gate distance, gate topology, eld and source/drain electrode insulation on transistor performance are investigated. Best ON=OFF ratios are measured with probe-gate devices for both insulated and uninsulated source/drain electrodes. Performance of probe-gate devices with uninsulated source/drain electrodes are superior to the ones with insulated source/drain due to absence of parasitic resistances related with the overlapping area of insulation layer. Planar-gate devices with source/drain insulation have lower ON=OFF ratios compared to probe-gate counterparts and device performance tends to deteriorate with increasing gate distance. Without source/drain electrode insulation, proper transistor operation is not obtained with planar-gate devices. Measurement results are in agreement with theoretical models. Inverters and ring oscillators are realized as circuit applications. WG-FET is a promising device platform for micro uidic applications where sensors and read-out circuits can be integrated at transistor level. | |
| dc.format.extent | 30 cm. | |
| dc.format.pages | xxv, 142 leaves ; | |
| dc.identifier.other | EE 2017 S66 PhD | |
| dc.identifier.uri | https://digitalarchive.library.bogazici.edu.tr/handle/123456789/13141 | |
| dc.publisher | Thesis (Ph.D.) - Bogazici University. Institute for Graduate Studies in Science and Engineering, 2017. | |
| dc.subject.lcsh | Transistors -- Mathematical models. | |
| dc.title | Realization and modeling of water-gated field effect transistors (WG-FET) using 16-NM-THICK single crystalline silicon film and their circuit applications |
Files
Original bundle
1 - 1 of 1