Second order sigma delta modulator architecture with low voltage swing at the output of the first integrator

Abstract

The technological improvements in digital Very Large Scale Integration (VLSI) circuits increase the need of analog digital converter with high performance and lower power consumption. Primarily, the oversampling techniques such as sigma delta modulation should be chosen instead of Nyquist rate analog digital converters to satisfy this need. Because sigma delta modulation combines oversampling, quantization noise shaping and digital filtering in order to achieve high performance. Also, the output swing and the speed performance of the op-amps which are utilized in the modulators should be optimized for low voltage and high speed applications. In this thesis, first of all, basic concepts of oversampling analog digital converter are explained and similar works which had been done before are examined. After that, a new low power second order sigma delta modulator in Mentor Graphics environment is proposed. To reduce the voltage swing at the output of first integrator as much as possible is the purpose of the research. Moreover, the proposed sigma delta modulator is compared to similar work in this area and it is shown that it has the lowest voltage swing at the first integrator output. As a result of the reduction of the voltage swing, op-amps with less power consumption or an inverter as an op-amp can be used instead of ideal op-amps in the project; and, this will provide less power consumption in the whole circuit. All sigma delta modulator architectures are designed with using ideal op-amp, real op-amp, differential amplifier and an inverter respectively in order to find the architecture that consumes the minimum power.